PDF Standards JEDEC JESD251A

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This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a master interface having a low signal count and high data transfer bandwidth with access to multiple sources of slave devices compliant with the interface. It is also, intended for use by peripheral developers or vendors interested in providing slave devices compliant with the standard, including non-volatile memories, volatile memories, graphics peripherals, networking peripherals, FPGAs, sensors, etc. Item 1775.59 and 19-395.

Product Details

Published:

02/01/2020

Number of Pages:

78

File Size:

1 file , 1.7 MB

Redline File Size:

2 files , 7.4 MB

Note:

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