PDF Standards IEC 60822 Ed. 1.0 b:1988

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The VSB bus was designed to meet the needs of multiprocessor systems based on high-performance 32-bit microprocessors built up from board assemblies. lt includes a high-speed asynchronous data transfer bus allowing masters to direct the transfer of binary data to and from slaves according to 4 kinds of cycles: address-only, single-transfer, block-transfer and interrupt-acknowledge cycles. It also includes an arbitration bus enabling arbiter modules and/or requester modules to coordinate the use of the data-transfer bus according to two arbitration methods (series or parallel). Note: -For the price of this publication, please consult the ISO/IEC price-code list.

Product Details

Edition:

1.0

Published:

12/30/1988

Number of Pages:

311

File Size:

1 file , 11 MB

Note:

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